The present disclosure relates to semiconductor structures, and particularly to nanowire tunnel field effect transistors.
Tunnel field effect transistors (TFETs) have emerged as an alternative for conventional complementary metal oxide semiconductor (CMOS) devices by enabling the supply voltage scaling in ultra-low power, energy efficient computing, due to their sub-60 mV/decade sub-threshold slope. TFETs possess unique device characteristics such as an asymmetrical source/drain design that induces uni-directional conduction and enhances the on-state Miller capacitance effect, thus enabling steep switching at low voltages. TFETs require low bandgap materials, steep tunneling junctions and improved electrostatics. Nanowire TFETs are attractive for low power, high density applications since nanometer scaled wires inherently provide excellent electrostatic control of the device. Therefore, methods for fabrication lateral heterostructure nanowire TFETs are needed.